I. Field
The present disclosure relates generally to electronics circuits, and more specifically to a delay circuit.
II. Background
A synchronous circuit such as a flip-flop or a latch may receive a data signal from one source and a clock signal from another source. The data and clock signals may have different propagation delays and may not be time aligned at the synchronous circuit. It may be desirable to delay the clock signal and/or the data signal by a proper amount so that these signals are time aligned. This may then allow the synchronous circuit to operate at a faster rate and/or achieve more timing margins, both of which are desirable.